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IDT5T9050 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
INDUSTRIAL TEMPERATURE RANGE
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFERTM JR.
FEATURES:
* * * * * * * * * *
IDT5T9050
DESCRIPTION:
Optimized for 2.5V LVTTL Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < 300 (max) High speed propagation delay < 1.8ns. (max) Up to 200MHz operation Very low CMOS power levels Hot insertable and over-voltage tolerant inputs 1:5 fanout buffer 2.5V VDD Available in TSSOP package
The IDT5T9050 2.5V single data rate (SDR) clock buffer is a single-ended input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. Multiple power and grounds reduce noise.
* Clock and signal distribution
APPLICATIONS:
FUNCTIONAL BLOCK DIAGRAM
GL G
O U TPUT C O N TR O L
Q1
O U TPUT C O N TR O L
Q2
A
O U TPUT C O N TR O L
Q3
O U TPUT C O N TR O L
Q4
O U TPUT C O N TR O L
Q5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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OCTOBER 2002
DSC-5958/17
(c) 2002 Integrated Device Technology, Inc.
IDT5T9050 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD Description Power Supply Voltage Input Voltage Output Voltage Storage Temperature Junction Temperature Max -0.5 to +3.6 -0.5 to +3.6 -0.5 to VDD +0.5 -65 to +165 150 Unit V V V C C VI VO TSTG TJ
GL VDD GND G V DD Q1 GND A Q5 V DD GND VDD V DD NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND VDD GND GND VDD Q2 GND Q3 Q4 VDD GND GND VDD NC
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1) (TA = +25C, F = 1.0MHz)
Symbol CIN Parameter Input Capacitance Min Typ. 6 Max. Unit pF
--
--
TSSOP TOP VIEW
NOTE: 1. This parameter is measured at characterization but not tested.
RECOMMENDED OPERATING RANGE
Symbol TA VDD Description Ambient Operating Temperature Internal Power Supply Voltage Min. -40 2.3 Typ. +25 2.5 Max. +85 2.7 Unit C V
PIN DESCRIPTION
Symbol A G GL Qn VDD GND I/O I I I O Type LVTTL LVTTL LVTTL LVTTL PWR PWR Description Clock input Gate control for Qn outputs. When G is LOW, these outputs are enabled. When G is HIGH, these outputs are asynchronously disabled to the level designated by GL(1). Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW. Clock outputs Power supply for the device core, inputs, and outputs Power supply return for power
NOTE: 1. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
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IDT5T9050 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(1)
Symbol IIH IIL VIK VIN VIH VIL VOH VOL Parameter Input HIGH Current Input LOW Current Clamp Diode Voltage DC Input Voltage DC Input HIGH(2) DC Input LOW(3) Output HIGH Voltage Output LOW Voltage Test Conditions VDD = 2.7V VI = VDD/GND VDD = 2.7V VI = GND/VDD VDD = 2.3V, IIN = -18mA Min. -- -- -- - 0.3 1.7 -- VDD - 0.4 VDD - 0.1 -- -- Typ.(4) -- -- - 0.7 Max 5 5 - 1.2 +3.6 -- 0.7 -- -- 0.4 0.1 Unit A V V V V V V V V
IOH = -12mA IOH = -100A IOL = 12mA IOL = 100A
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. Voltage required to maintain a logic HIGH. 3. Voltage required to maintain a logic LOW. 4. Typical values are at VDD = 2.5V, +25C ambient.
POWER SUPPLY CHARACTERISTICS
Symbol IDDQ IDDD ITOT Parameter Quiescent VDD Power Supply Current Dynamic VDD Power Supply Current per Output Total Power VDD Supply Current Test Conditions(1) VDD = Max., Reference Clock = LOW Outputs enabled, All outputs unloaded VDD = Max., CL = 0pF VDD = 2.5V., FREFERENCE CLOCK = 100MHz, CL = 15pF VDD = 2.5V., FREFERENCE CLOCK = 200MHz, CL = 15pF Typ. 1 100 50 75 Max 1.5 150 65 100 Unit mA A/MHz mA
NOTE: 1. The termination resistors are excluded from these measurements.
INPUT AC TEST CONDITIONS
Symbol VIH VIL VTH tR, tF Parameter Input HIGH Voltage Input LOW Voltage Input Timing Measurement Reference Level(1) Input Signal Edge Rate(2) Value VDD 0 VDD/2 2 Units V V V V/ns
NOTES: 1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
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IDT5T9050 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(4)
Symbol Skew Parameters tSK(O) tSK(P) tSK(PP) Propagation Delay tPLH tPHL tR tF Output Rise Time (20% to 80%) Output Fall Time (20% to 80%) 350 350 -- -- -- -- -- -- -- -- 850 850 200 3.5 3 ps ps Parameter Same Device Output Pin-to-Pin Skew(1) Pulse Skew(2) Part-to-Part Skew(3) Propagation Delay A to Qn Min. -- -- -- -- Typ. -- -- -- -- Max 25 300 300 1.8 Unit ps ps ps ns
fO Frequency Range Output Gate Enable/Disable Delay tPGE tPGD Output Gate Enable to Qn Output Gate Enable to Qn Driven to GL Designated Level
MHz
ns ns
NOTES: 1. Skew measured between all outputs under identical input and output transitions and load conditions on any one device. 2. Skew measured is the difference between propagation delay times tPHL and tPLH of any output under identical input and output transitions and load conditions on any one device. 3. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD levels and temperature. 4. Guaranteed by design.
AC TIMING WAVEFORMS
1/fo
tW A
tW
VIH VTH VIL
tPLH Qn
tPHL VOH VTH VOL
tSK(O) Qm
tSK(O) VOH VTH VOL
Propagation and Skew Waveforms
NOTE: Pulse Skew is calculated using the following expression: tSK(P) = | tPHL - tPLH | where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not valid measurements for this calculation because they are not taken from the same pulse.
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IDT5T9050 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
INDUSTRIAL TEMPERATURE RANGE
VIH A VTH VIL
VIH GL VTH VIL tPLH G
VIH VTH VIL tPGD tPGE VOH VTH VOL
Qn
Gate Disable/Enable Showing Runt Pulse Generation
NOTE: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their G signal to avoid this problem.
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IDT5T9050 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUIT AND CONDITIONS
VDD
VDD
VDD
R1 VIN 3 inch, ~50 Transmission Line A
R1
D.U.T.
Qn
Pulse Generator
R2
CL
R2
Test Circuit for Input/Output
INPUT/OUTPUT TEST CONDITIONS
Symbol VTH R1 R2 CL VDD = 2.5V 0.2V VDD / 2 100 100 15 Unit V pF
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IDT5T9050 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Package
I
-40C to +85C (Industrial)
PG
Thin Shrink Small Outline Package
5T9050 2.5V Single Data Rate 1:5 Clock Buffer Terabuffer Jr.
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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